Error correcting memory system

Details Error correcting memory system Error correcting memory system

1994-01-21

2000-03-14

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

H03M 1300

Patent

active

060386924

ABSTRACT:
An error correcting memory system, which writes and reads m-bit data and an error marking n-bit pointer by a predetermined rule, includes a first memory for m-bit data; a second memory for the n-bit pointer, an address generating unit for generating address signals for the first and second memories by a predetermined rule, and a writing/reading control signal generating unit for generating the respective writing and reading control signals of the first and second memories by receiving the writing and reading control signals and responding to a data/pointer differentiating signal. Therefore, the memory size of the error correcting memory system can be reduced.

REFERENCES:
patent: 4719628 (1988-01-01), Ozaki et al.
Digital Communications, Second Edition by John G. Proakis .COPYRGT. 1989 by McGraw-Hill, Inc. pp. 440-442.

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