Apparatus and method for designing a test and modeling system fo

Details Apparatus and method for designing a test and modeling system fo Apparatus and method for designing a test and modeling system fo

1997-12-18

2000-06-27

Teska, Kevin J.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 7, 716 8, 703 14, 703 17, 703 20, G06F 1750

Patent

active

060802030

ABSTRACT:
An arrangement for designing a testing modeling system provides a testing hierarchy, where non-standard device elements having internal memory and logic structures are modeled by partitioning the device element into a recognizable memory model and a recognizable logic model separate from the memory model. The segregated models are then verified for accuracy using existing design and simulation tool and with comparison to existing hardware implementations. Once the revised models have been verified, the new models can be stored in a model library for future use.

REFERENCES:
patent: 5515376 (1996-05-01), Murthy et al.
patent: 5684808 (1997-11-01), Valind
patent: 5862149 (1999-01-01), Carpenter et al.
Kawaguchi et al, "A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm", IEEE Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, pp. 57-60, Jan. 1997.
Fang et al, "A Hierarchical Functional Structuring and Partitioning Approach for Multiple-FPGA Implementations", 1996 IEEE/ACM International Conference on Computer-Aided Design, pp. 638-643, Nov. 1996.
Hosokawa et al, "A Design for Testability Method Using RTL Partitioning", IEEE Proceedings of the Fifth Asian Test Symposium, pp. 88-93, Nov. 1996.

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