Digital delay unit with interleaved memory

Details Digital delay unit with interleaved memory Digital delay unit with interleaved memory

1988-03-17

1989-07-18

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, 36523004, 365233, 365236, 340799, G11C 700, G11C 800

Patent

active

048499374

ABSTRACT:
A first memory cell array (84) has an even address space and a second memory cell array 94 has an odd address space. The memory cell arrays (84, 94) are alternately accessed by even address signals generated from an address counter (81) and odd address signals generated from an address counter (91) so that the data stored in the memory cell arrays are alternately read while new input data are written in the accessed memory cells.

REFERENCES:
patent: 3866180 (1975-02-01), Willette
patent: 4122489 (1978-10-01), Bolger et al.
patent: 4171538 (1979-10-01), Sheller
patent: 4361869 (1982-11-01), Johnson et al.
patent: 4513372 (1985-04-01), Ziegler et al.
patent: 4740923 (1988-04-01), Kaneko et al.
"Television Gakkaishi (The Journal of the Institute of Television Engineers of Japan)", vol. 39, No. 3 (1985), pp. 250 to 252.

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