CMOS processing employing removable sidewall spacers for indepen

Details CMOS processing employing removable sidewall spacers for indepen CMOS processing employing removable sidewall spacers for indepen

1997-09-05

1998-12-08

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438230, 438231, 438232, 438303, 438305, 438307, 438308, 257336, 257371, H01L 218238

Patent

active

058468579

ABSTRACT:
N- and P-channel transistor characteristics are independently optimized for CMOS semiconductor devices with design features of 0.25 microns and under. Removable second sidewall spacers are formed on the N-channel transistor gate electrode having first sidewall spacers thereon. Ion implantation is conducted to form N-type moderately/heavily doped implants followed by activation annealing. The second sidewall spacer is then removed from the P-channel transistor leaving first sidewall spacers thereon serving as an ion implantation mask for the P-type lightly doped implants. Subsequently, third sidewall spacers are formed on the P-channel gate electrode having first sidewall spacers thereon followed by ion implantation to form the P-type moderately or heavily doped implants, with subsequent activation annealing. Embodiments enable complete independent control of the channel lengths of the N- and P-channel transistors by varying the width of the first, second and third sidewall spacers.

REFERENCES:
patent: 4891326 (1990-01-01), Koyanagi
patent: 4968639 (1990-11-01), Bergonzoni
patent: 5030582 (1991-07-01), Miyajima et al.
patent: 5696016 (1997-12-01), Chen et al.

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