Planarized metallurgy structure for a semiconductor and process

Details Planarized metallurgy structure for a semiconductor and process Planarized metallurgy structure for a semiconductor and process

1998-03-20

1999-05-18

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257390, 257401, 257503, 257773, 257786, H01L29/72

Patent

active

059052899

ABSTRACT:
A method for fabricating a metallurgy system is described wherein a first level of metallurgy is formed, having a plurality of close uniformly spaced conductive line of a predetermined width, and wherein there are included larger gaps between the conductive lines. The areas in the larger gaps are filled with dummy lines, where the gap is equal to or greater than three times the feature size or alternatively the width of the conductive lines.

REFERENCES:
patent: 5077234 (1991-12-01), Scoopo et al.
"Improved Sub-Micron Inter-Metal Dielectric Gap-Filling Using TEOS/Ozone APCVD", Microelectronics Manufacturing Technology, pp. 22-27, Jan. 1992.

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