Read-only memory with few programming signal lines

Details Read-only memory with few programming signal lines Read-only memory with few programming signal lines

1991-04-04

1993-06-29

Sikes, William L.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518907, 36518912, 365194, 365219, 307465, G11C 700, G11C 1140

Patent

active

052240720

ABSTRACT:
A signal-generating circuit receives a program signal and generates an output enable signal, a control signal, and a latch signal. In response to the output enable signal, a programmable read-only memory outputs data onto a data bus. In response to the control signal, a three-state buffer outputs data from a first register to the data bus; the data can then be stored in the programmable read-only memory by input of a chip enable signal. In response to the latch signal, a second register latches data output from the programmable read-only memory onto the data bus. An equality checker compares the contents of the first and second registers and generates an equal signal indicating whether they are equal.

REFERENCES:
patent: 4410965 (1983-10-01), Moore
patent: 4506348 (1985-03-01), Miller et al.
patent: 4628480 (1986-12-01), Floyd
patent: 4633441 (1986-12-01), Ishimoto
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 5119330 (1992-06-01), Tanagawa
Stofka, Design Ideas-"Serial/parallel shifts increase RAM speed", Jan. 7, 1981, pp. 198 & 200.

Affiliated with

Also associated with

Rating

Read-only memory with few programming signal lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read-only memory with few programming signal lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read-only memory with few programming signal lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1761023