Method of fabricating high density buried bit line flash EEPROM

Details Method of fabricating high density buried bit line flash EEPROM Method of fabricating high density buried bit line flash EEPROM

1999-03-18

2000-11-28

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438221, 438222, 438259, 438262, 438270, 438280, 438263, H01L 21336

Patent

active

061534676

ABSTRACT:
A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface. After refilling a plurality of trenches with a conductive impurity doped silicon layer, a planarization process such as CMP is followed to form a plain surface using the gate dielectric layer as an etching stopped layer. A stacked ONO layer is then deposited as an interpoly dielectric layer; and finally another a conductive impurity doped polysilicon layer is formed and patterned to be as word lines.

REFERENCES:
patent: 4981812 (1991-01-01), Nishizaka
patent: 5208179 (1993-05-01), Okazawa
patent: 5340769 (1994-08-01), Miyamoto
patent: 5744847 (1998-04-01), Wen
patent: 5872043 (1999-02-01), Chen
patent: 5880007 (1999-03-01), Varian et al.
patent: 5970341 (1999-10-01), Lin et al.
patent: 6008079 (1999-12-01), Wu
patent: 6048765 (2000-04-01), Wu
patent: 6084264 (2000-07-01), Wu

Affiliated with

Also associated with

Rating

Method of fabricating high density buried bit line flash EEPROM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating high density buried bit line flash EEPROM , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating high density buried bit line flash EEPROM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1724669