Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-12
2000-11-28
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438398, 438735, H01L 218242
Patent
active
061534668
ABSTRACT:
The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-SI on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.
REFERENCES:
patent: 5726085 (1998-03-01), Crenshaw et al.
patent: 5976931 (1999-11-01), Yew et al.
"A new stacked SMVP (Surrounded Micro Villus Patterning) Cell for 256 Mega and 1 Giga bit DRAMs", S.P. Sim et al., International Conference on Solid State Devices and Materials, 1993. pp. 886-888.
Watanabe, et al., "Device Application and Structure Observation for Hemispherical-Grained Si," J. Appl. Phys. 71 (7), pp. 3538-43, Apr. 1, 1992.
Fazan, et al., "Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked DRAMs," IEEE, pp. 90-663-666, (1990).
Sakao, et al., "A Capacitor-Over-Bit-Line (COB) Cell With a Hemispherical-Grain Storage Node for 64Mb DRAMs," IEEE, pp. 90-655-658, (1990).
Rosato, et al., "Ultra-High Capacitance Nitride Films Utilizing Surface Passivation on Rugged Polysilicon," J. Electrochem. Soc., vol. 139, No. 12, pp. 3678-82 (Dec. 1992).
Lur Water
Sun Shih-Wei
Yew Tri-Rung
Anya Igwe U.
Smith Matthew
United Microelectronics Corp.
LandOfFree
Method for increasing capacitance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for increasing capacitance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for increasing capacitance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1724664