EPROM manufacturing process having a floating gate with a large

Details EPROM manufacturing process having a floating gate with a large EPROM manufacturing process having a floating gate with a large

1997-08-18

1999-06-22

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438594, H01L 218247

Patent

active

059151773

ABSTRACT:
The method for forming a "U" shaped floating gate 120a with high vertical projections 120c, begins by forming a dielectric layer 110 over the substrate 100. A photoresist layer 112 is then formed on the dielectric layer 110 and patterned to form a first opening 113. The first opening 113 exposes the dielectric layer 110. In an important step, a polymer layer 114 is formed over the photoresist layer 112 and on the vertical sidewalls of the first opening 113 thereby forming a second opening 115. The second opening 115 has a smaller width than that of the first opening 113. The dielectric layer 110 is anisotropically etched thru the second opening 115 thereby forming a third opening 116 in the dielectric layer 110. The photoresist layer 112 and the polymer layer 114 are now removed. The exposed substrate within the third opening 116 is thermally oxidized to form a tunnel oxide layer 118. A first polysilicon layer 120 is formed conformally on the resultant surface and in the third opening. The first polysilicon layer is chemically mechanically polished, thereby forming the U-shaped floating gate 120a in the third opening 116. An intergate dielectric layer 122 and a control gate 124A are then formed on the floating gate 120a to complete the EPROM.

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