Method and apparatus for powering down an integrated circuit tra

Details Method and apparatus for powering down an integrated circuit tra Method and apparatus for powering down an integrated circuit tra

1997-06-19

1998-11-24

Sheikh, Ayaz R.

G06F 132

Patent

active

058420290

ABSTRACT:
A method and apparatus for powering down a microprocessor in a computer system. The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the processor in response to global clock signal of the computer system. The microprocessor includes circuitry for processing data synchronous with the core clock signals. The method and circuit also includes circuitry for placing the processor in a reduced power consumption state in response to the execution of a power down instruction. In this manner, the computer system reduces power consumption.

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