Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-02-12
2000-03-14
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438279, 438593, 438595, 438592, 438303, 438634, 438261, 257382, 257383, 257412, 257900, H01L 218238, H01L 21336, H01L 213206, H01L 2976, H01L 27088
Patent
active
060372281
ABSTRACT:
A method of fabricating a self-aligned contact window is described. A gate oxide layer, a conductive layer, a first oxide layer and an undoped polysilicon layer are successively formed on a substrate. These layers above are patterned to form a gate structure. A water clean step is performed, producing a recess in the first oxide layer. A second oxide layer is thermally formed on the surface of the gate structure. An undoped polysilicon spacer is formed on the sidewall of the gate structure and a portion of the undoped polysilicon spacer extends into the recess of the first oxide layer. A dielectric layer is formed over the substrate and using the undoped polysilicon spacer as an etching stop, a self-aligned contact window is formed to expose the source/drain region.
REFERENCES:
patent: 5491100 (1996-02-01), Lee et al.
patent: 5545578 (1996-08-01), Park et al.
patent: 5559049 (1996-09-01), Cho
patent: 5897353 (1999-04-01), Kim et al.
Niebling John F.
Pompey Ron
United Microelectronics Corp.
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