Method of manufacturing semiconductor integrated circuit device

Details Method of manufacturing semiconductor integrated circuit device Method of manufacturing semiconductor integrated circuit device

1997-11-13

2000-03-14

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438256, 438656, H01L 218242

Patent

active

060372079

ABSTRACT:
In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

REFERENCES:
patent: 5320976 (1994-06-01), Chin et al.
patent: 5387532 (1995-02-01), Hamamoto et al.
patent: 5438008 (1995-08-01), Ema
patent: 5604365 (1997-02-01), Kajigaya et al.
Kang et al. Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMS, IEDM-1994.

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