Redundancy circuit and method of a semiconductor memory device

Details Redundancy circuit and method of a semiconductor memory device Redundancy circuit and method of a semiconductor memory device

1995-11-17

1999-11-30

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

059954221

ABSTRACT:
The present invention provides a redundancy circuit in a semiconductor memory device which has spare memory cells which can store information that can be substituted for data of defective memory cells after the completion of the manufacturing process. If addresses designating the defective memory cells are externally input, the redundancy circuit generates a defective cell relief address signal which corresponds to the address designating the defective memory cell and is used to prevent defective data stored in normal memory cells from being output and causes correction data, to be substituted for the defective data output in correspondence with the defective cell relief address.

REFERENCES:
patent: 5258953 (1993-11-01), Tsujimoto
patent: 5379259 (1995-01-01), Fujita
patent: 5414659 (1995-05-01), Ito
patent: 5416740 (1995-05-01), Fujita et al.

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