Semiconductor device with impurity layer as channel stopper imme

Details Semiconductor device with impurity layer as channel stopper imme Semiconductor device with impurity layer as channel stopper imme

1998-09-10

1999-11-30

Fahmy, Wael M.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438217, 438225, 438289, 438448, 438450, 438220, H01L 21336

Patent

active

059941901

ABSTRACT:
A semiconductor device includes a first conductivity type low concentration impurity layer provided around a thick silicon oxide film, which is formed for element isolation in a first conductivity type element region as a surface region in a semiconductor substrate, and a second conductivity type impurity layer which is provided immediately under at least the thick silicon oxide film. The second conductivity type impurity layer constitutes a channel stopper to enhance the effect of element isolation. The first conductivity type low concentration impurity layer has an effect of improving the P-N junction breakdown voltage of an active region in the first conductivity type element region, and suppresses the narrow channel effect of a MOS transistor in the first conductivity type element region.

REFERENCES:
patent: 5344787 (1994-09-01), Nagalingam et al.
patent: 5378650 (1995-01-01), Kimura
patent: 5484742 (1996-01-01), Urai
patent: 5556798 (1996-09-01), Hong
patent: 5599731 (1997-02-01), Park
patent: 5633191 (1997-05-01), Chao
patent: 5747372 (1998-05-01), Lim
patent: 5786265 (1998-07-01), Hwang et al.

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