Reduced mask process for manufacture of MOS gated devices using

Details Reduced mask process for manufacture of MOS gated devices using Reduced mask process for manufacture of MOS gated devices using

1995-12-11

1998-07-21

Dutton, Brian

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438135, H01L 21265

Patent

active

057834741

ABSTRACT:
A process for forming a MOS gated device in which an oxide layer grown on a silicon surface is first patterned to form windows for implantation of P++ regions. Following implantation of the P++ regions, the oxide is completely etched off, and a thermal oxide layer is grown on the wafer surface. Since oxide grows thicker over the highly doped P++ region, the result is a pattern of thick and thin oxide layers atop the silicon surface. Polysilicon is then patterned atop the oxide layer with a critical alignment step to the thin oxide layers in the process. Boron is implanted through both the thick and thin regions of the oxide which are exposed by the polysilicon mask to form P type base regions and P type guard rings in the silicon. Arsenic is thereafter implanted at an energy at which arsenic atoms significantly penetrate only the thin oxide exposed by the polysilicon to form self-aligned source regions in the P type base regions previously formed. A contact opening mask which is critically aligned to the polysilicon mask forms openings for making contact to the silicon. The device is completed using non-critical alignment masking steps. Additional embodiments with modified process sequences are also disclosed.

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patent: 5164327 (1992-11-01), Maruyama
patent: 5187117 (1993-02-01), Zommer
patent: 5465000 (1995-11-01), Williams

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