Elevated channel MOSFET

Details Elevated channel MOSFET Elevated channel MOSFET

1998-09-29

2000-11-07

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438289, 438300, 438682, H01L 218238

Patent

active

061435937

ABSTRACT:
The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized process order. The process flow of the present invention provides for the implantation and thermal processing of the wells and junctions prior to the growth of a channel or the deposition of a gate stack. By implanting and annealing the wells and junctions prior to the formation of the channel and gate, the present invention allows a greater variety of materials to be utilized as the channel and gate materials than are available under process flows currently known; undoped materials may be used to form the channel, metal oxides and similar materials with large dielectrics may be used to form a gate stack, and barrier metals and pure metals (copper, tungsten, etc.) may be used as gate electrodes. The present invention also provides for the selective epitaxial growth of a channel material elevated above the surface of a wafer containing a well and junctions. By providing an elevated channel, higher mobility may be achieved; thereby enabling a higher current flow at a lower voltage through a semiconductor device.

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ULSI Technology, C. Y. Lu and W. Y. Lee, Chap. 9, pp. 472-525 (1996).
Ray, S.K., et al., "Novel SiGeC Channel Heterojunction PMOSFET", International Electron Devices Meeting (IEDM), US, New York, IEEE, 1996, pp. 261-264.

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