Method of fabricating deep submicron MOSFET with narrow gate len

Details Method of fabricating deep submicron MOSFET with narrow gate len Method of fabricating deep submicron MOSFET with narrow gate len

1996-09-11

1998-09-22

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438291, 438299, 438526, 438585, 438947, H01L 21336

Patent

active

058113398

ABSTRACT:
The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.

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S.A. Abbas et al., IBM Tech. Discl. Bulletin, 20(4)(1977)1376 "Extending the minimal dimensions of photolithographic . . . ", Sep. 1977.

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