Dynamic memory array with quasi-folded bit lines

Details Dynamic memory array with quasi-folded bit lines Dynamic memory array with quasi-folded bit lines

1984-07-26

1987-10-20

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1140

Patent

active

047018852

ABSTRACT:
A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a quasi-folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of the two segments to be connected to one of the two bit lines. Instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.

REFERENCES:
patent: 4301518 (1981-11-01), Klaas
patent: 4494220 (1985-01-01), Dumbri et al.

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