Active solid-state devices (e.g. – transistors – solid-state diode – With shielding
Patent
1999-08-02
2000-05-02
Clark, Sheila V.
Active solid-state devices (e.g., transistors, solid-state diode
With shielding
257508, 257699, 257724, 257783, 257604, H01L 23552
Patent
active
06057593&
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates in general to electronic engineering and more specifically to a power microwave hybrid integrated circuit.
BACKGROUND OF THE INVENTION
One prior-art power microwave hybrid integrated circuit is known, the circuit comprises a metal base having through holes for naked semiconductor chips and an insulating polymer film joined to the metal base and having through holes mating with those of the base. A second insulating film is placed on and held to the first insulating film, said second film having through holes of a smaller size mating with the holes in the first polymer film. The naked semiconductor chips are mounted on the back side of the second polymer film with their bonding pads towards the films (i.e., upwards). A second commutation level is arranged on the face side of the second polymer film and is electrically connected to the chip bonding pads through the holes in the second polymer film (JP, B. 57-036746).
The integrated circuit discussed above is possessed of a low heat dissipation rate due to a small chip-to-metal base heat contact area.
One more prior-art power microwave hybrid integrated circuit is known, the circuit comprises a metal base having recesses, naked semiconductor chips disposed in and fixed to said recesses with a binder, a dielectric multilayer board having a topological metallization pattern on its face side and through holes electrically connecting the chip bonding pads to the topological metallization pattern of the board and filled with an electrically conducting material. The chips are slightly sunk into the metal base, and the planarization of the circuit is attained by applying, polymer dielectric layers of the board (cf. "Electronic devices on chip integral circuits", edited by I. N. Vozhenin, 1985, "Radio i Sviaz" Publishers, Moscow, p.261 (in Russian).
The circuit mentioned above is possessed of an inadequate heat conductance and low electrical characteristics.
SUMMARY OF THE INVENTION
The principal object of the present invention is to provide a power microwave hybrid integrated circuit having such a constructive arrangement that allows to improve electrical and heat dissipating characteristics thereof.
The foregoing object is accomplished due to the fact that in a power microwave hybrid integrated circuit, comprising a metal base having recesses, naked semiconductor chips disposed in and fixed to said recesses with a binder, a dielectric board having, a topological metallization pattern on its face side and holes electrically connecting the chip bonding pads to the topological metallization pattern of the board and filled with an electrically conducting material, according to the invention, the depth of the recesses in the metal base is selected so that the face surface of the chip and the metal base are coplanar, the dielectric board has a shield grounding metallization on the back side thereof at the places adjoining the metal base, the metal base is sealingly joined and electrically connected to the shield grounding metallization of the board, and the interconnecting holes are sealingly filled with an electrically conducting material, the spacing between the side surface of the chips and the side surfaces of the recesses in the base being of 0.001 to 0.2 mm.
The chip bonding pads to be grounded may be electrically connected directly to the shield grounding metallization of the board through beam leads 0.002 to 0.1 mm high.
The beam leads may be formed on the back side of the board.
Locating the chip face surface and the surface of the metal base complanar, providing the shield grounding metallization and sealingly electrical connection of the metal base to the shield grounding metallization, as well as filling, the interconnecting holes in the board with an electrically conducting material, ensures a hermetic sealing of the semiconductor chips.
Limiting the spacing between the chip side surface and the side faces of the recesses in the base from below is dictated by irregularities of the mating surfaces, w
REFERENCES:
patent: 3431468 (1969-03-01), Huffman
patent: 3748546 (1973-07-01), Allison
patent: 3903590 (1975-09-01), Yokogawa
patent: 4907062 (1990-03-01), Fukushima
patent: 5151769 (1992-09-01), Immorlica, Jr. et al.
patent: 5315486 (1994-05-01), Fillion et al.
Iovdalsky Viktor Anatolievich
Moldovanov Jury Isaevich
Clark Sheila V.
Samsung Electronics Co,. Ltd.
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