Process for making crosspoint memory devices with cells having a

Details Process for making crosspoint memory devices with cells having a Process for making crosspoint memory devices with cells having a

1998-08-07

2000-05-02

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438263, 438257, 257316, H01L 2700, H01L 21336

Patent

active

060571926

ABSTRACT:
A process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide is disclosed. The process includes the steps of growing a thin layer of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer; photolithographing with a Poly1 mask to define a plurality of parallel floating gate regions in the stack structure; self-aligned etching of the stack structure, above the active areas, to define continuous bit lines; and implanting, to confer predetermined conductivity on the active areas. Advantageously, the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate, is discontinued before the field oxide is removed, and the implantation step is carried out in the presence of field oxide over the source active areas.

REFERENCES:
patent: 4957877 (1990-09-01), Tam et al.
patent: 5087584 (1992-02-01), Wada et al.
patent: 5409854 (1995-04-01), Bergemont
patent: 5726470 (1998-03-01), Sato
patent: 5960283 (1997-10-01), Sato

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