Method of fabricating a dram cell with a plurality of vertical e

Details Method of fabricating a dram cell with a plurality of vertical e Method of fabricating a dram cell with a plurality of vertical e

1996-10-25

1998-04-28

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438657, H01L 218242

Patent

active

057443904

ABSTRACT:
Fabricating a DRAM memory cell with increased capacitance by increasing the surface area of a storage electrode of a storage capacitor includes forming transfer transistor having a gate electrode and source-drain electrode areas on a semiconductor substrate. First, second and third insulating layers are formed in sequence on the semiconductor substrate and the transfer transistor. The third, second and first insulating layers are selectively etched through to form a contact opening exposing one of the source-drain electrode areas as a contact area. An upper portion of the third insulating layer is etched to form a plurality of first trenches. A first conductive layer is formed over the insulating layer filling the contact opening and the first trenches. An upper portion of the first conductive layer is etched to form a plurality of second trenches, and selectively etched to define a pattern area of a storage electrode of a capacitor. The storage electrode includes a vertical frame which contacts the contact area through the contact opening, and a horizontal plate having a plurality of extending areas which extend out vertically therefrom. Using the second insulating layer as an etching stop, the third insulating layer is removed by isotropic etching. A dielectric layer is formed on exposed surfaces of the storage electrode. A second conductive layer, which acts as an opposed electrode of the capacitor, is formed on the dielectric layer.

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