Pipelined memory having synchronous and asynchronous operating m

Details Pipelined memory having synchronous and asynchronous operating m Pipelined memory having synchronous and asynchronous operating m

1994-03-08

1995-01-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518904, 36523008, G11C 1300

Patent

active

053847377

ABSTRACT:
A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).

REFERENCES:
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Terry I. Chappell et al., "A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM", Feb. 1991 IEEE International Solid-State Circuits Conference, pp. 50, 51 & 288.

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