Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-05-20
2000-01-11
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060147644
ABSTRACT:
Apparatus and methods providing pattern chaining and looping in a circuit tester. The tester has a pattern data memory for storing multiple patterns and for storing a pattern chaining definition. Each pattern has pattern data for one or more test vectors. The pattern chaining definition specifies (i) a sequential order for the patterns and (ii) a location in the pattern data memory of each of the patterns. When the tester executes a functional test, the pattern chaining definition is read from the pattern data memory and used to locate each of the patterns, and the pattern data of each pattern is read to provide a test vector for each test period of the functional test. In another aspect, both a pattern program including one or more test vectors and a loop definition are stored in the pattern data memory. The pattern program defines an ordering for the test vectors, and the loop definition specifies a loop of test vectors. When the tester executes a functional test that includes the loop, the test vectors of the loop are read an indefinite number of times until a loop ending condition occurs. The first loop test vector of the loop need not be the initial test vector of the pattern program. In another aspect, the tester has chaining control registers including a start address register for pointing to a pattern chaining definition stored in the pattern data memory and a current pattern pointer register for pointing to a current pattern stored in the pattern data memory; a pattern data output sequencer; and a pattern data buffer memory coupled between the pattern data memory and the pattern data output sequencer.
REFERENCES:
patent: 4502127 (1985-02-01), Garcia et al.
patent: 4635096 (1987-01-01), Morgan
patent: 4639919 (1987-01-01), Chang et al.
patent: 4855681 (1989-08-01), Millham
patent: 5122988 (1992-06-01), Graeve
patent: 5151903 (1992-09-01), Mydill et al.
patent: 5212443 (1993-05-01), West et al.
patent: 5280486 (1994-01-01), Arkin et al.
patent: 5561765 (1996-10-01), Shaffer et al.
Chang, Ed, Sep. 22, 1986, "Trillium Test Techniques," Trillium Test Systems Applications Notes, as presented to the 4th IC Test Conference, Beijing, China (Sponsored by The Chinese Institute of Electronics).
Huston, Robert, Dec. 17, 1985, "Pattern Architecture," Trillium Test Systems Applications Notes.
Chew Teck Chiau
Graeve Egbert
West Burnell G.
Nguyen Hoa T.
Schlumberger Technologies Inc.
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