Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-01-15
2000-01-11
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060147636
ABSTRACT:
A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
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Dhong Sang Hoo
Hofstee Harm Peter
Nowka Kevin John
Silberman Joel Abraham
Dillon Andrew J.
International Business Machines - Corporation
Musgrove Jack V.
Nguyen Hoa T.
Salys Casimer K.
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