Test access port controller and a method of effecting communicat

Details Test access port controller and a method of effecting communicat Test access port controller and a method of effecting communicat

1997-10-29

1999-11-09

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

365201, G01R 3128

Patent

active

059833793

ABSTRACT:
There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.

REFERENCES:
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5448576 (1995-09-01), Russell
patent: 5570375 (1996-10-01), Tsai et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5781558 (1998-07-01), Inglis et al.
Standard Search Report dated Feb. 26, 1997.
IEEE Standard Test Access Port and Boundary--Scan Architecture , C.M. Maunder, IEEE Inc., May 21, 1990.

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