Sub-word line drivers for integrated circuit memory devices and

Details Sub-word line drivers for integrated circuit memory devices and Sub-word line drivers for integrated circuit memory devices and

1996-09-03

1998-06-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36523006, G11C 700

Patent

active

057611351

ABSTRACT:
An integrated circuit memory device includes an array of memory cells arranged into rows and columns. A main word line decoder receives a first portion of a row address and generates a main word line activation signal on a predetermined word line in response thereto. A word driver predecoder receives a second portion of the row address and generates a sub-row activation signal in response thereto. A sub-word line driver generates a sub-word line activation signal on an output node. This sub-word line driver includes a pull-down transistor, a pull-up transistor, and a driving transistor. The pull-down transistor electrically connects the output node to a ground terminal in response to an inverse of the sub-row activation signal. The pull-up transistor transfers the sub-row activation signal to the output node in response to the main word line activation signal. The driving transistor transfers the main word line activation signal to the output node in response to the sub-row activation signal. A sub-word line electrically connects the output node and a predetermined memory cell so that the predetermined memory cell is activated in response to the sub-word line activation signal.

REFERENCES:
patent: 5369619 (1994-11-01), Ohba
patent: 5373471 (1994-12-01), Saeki et al.
patent: 5381377 (1995-01-01), Bewick et al.
patent: 5461593 (1995-10-01), Kim
patent: 5596542 (1997-01-01), Sugibayashi et al.
patent: 5617369 (1997-04-01), Tomishima et al.
Sugibayashi et al., A 30-ns 256-mb DRAM with a Multidivided Array Structure,IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1092-1098.

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