Semiconductor processing method of fabricating field effect tran

Details Semiconductor processing method of fabricating field effect tran Semiconductor processing method of fabricating field effect tran

1996-02-22

1998-12-15

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438232, 438302, H01L 218238

Patent

active

058496157

ABSTRACT:
In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.

REFERENCES:
patent: 5147811 (1992-09-01), Skagami
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5401994 (1995-03-01), Adan
patent: 5500379 (1996-03-01), Odake et al.
patent: 5614432 (1997-03-01), Goto
D. Jung et. al., "A 0.25.mu.m CMOSFET Using Halo Implantation for 1Gb DRAM", Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials, Osaka, published, Sep. 1995, pp. 869-871.

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