Method of building an EPROM cell without drain disturb and reduc

Details Method of building an EPROM cell without drain disturb and reduc Method of building an EPROM cell without drain disturb and reduc

1997-09-29

1999-11-09

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438266, 36518502, 36518518, 36518526, 36518528, H01L 21336, G11C 1604

Patent

active

059813407

ABSTRACT:
A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

REFERENCES:
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 5049515 (1991-09-01), Tzeng
patent: 5471422 (1995-11-01), Chang et al.
patent: 5646060 (1997-07-01), Chang et al.
Chang, et al., U.S. application No. 08/603,939, filed on Feb. 20, 1996, now US Pat. 5,706,228.

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