Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1983-09-16
1986-04-15
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
307449, 307463, 365230, 365184, G11C 700, G11C 800
Patent
active
045832056
ABSTRACT:
A programmable memory circuit adapted to access a memory comprises a decoder responsive to address input signals, an access line, a transfer gate connected between the decoder and the access line, and a selective voltage supply circuit connected to the access line. The transfer gate is responsive to a read/write switch signal to connect the decoder to the access line in the read mode and disconnect the decoder from the access line in the write mode. The selective voltage supply circuit is also responsive to the read/write switch signal to provide on the access line different voltage levels in accordance with read/write mode. The access line assumes, in the read mode, one voltage level which is equal to the level of the output signal from the decoder and in the write mode the other voltage level.
REFERENCES:
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4264828 (1981-04-01), Perlegos et al.
patent: 4404659 (1983-09-01), Kihara et al.
patent: 4455629 (1984-12-01), Suzuki et al.
Stewart et al., "A 40ns CMOS E.sup.2 PROM", IEEE ISSCC Digest of Tech. Papers, Feb. 11, 1982, pp. 110-111, 303.
Gossage Glenn A.
Hecker Stuart N.
NEC Corporation
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