Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1983-08-04

1986-04-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1300

Patent

active

045832021

ABSTRACT:
In a semiconductor memory cell of the type in which memory cells are arranged in a matrix, the present invention discloses a novel construction of a word line which interconnects a plurality of memory cell in one row. Each word line is divided at least at one point into a first word line and a second word line which are electrically isolated from each other and a first switching circuit is interconnected between the first and second word lines. When each word line is selected, the first switching circuit is responsive to a select signal propagated from the first word line so as to increase the potential of the second word line to a predetermined select level and when each word line is deselected, the first switching circuit causes the potential of the second word line to a deselect level in synchronism with a deselect signal. A second switching circuit is connected to the input end or the terminal end of the second word line so as to cause the potential of the second word line to a deselect level in synchronism with a deselect signal which is different from said first mentioned select signal.

REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.
patent: 4044341 (1977-08-01), Stewart et al.

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