Method of forming vias

Details Method of forming vias Method of forming vias

1995-05-09

1997-01-14

Fourson, George

Fishing, trapping, and vermin destroying

437235, 437978, 437228, 148DIG43, 148DIG118, 1566571, H01L 21441

Patent

active

055939210

ABSTRACT:
A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.

REFERENCES:
patent: 4523372 (1985-06-01), Balda et al.
patent: 4894351 (1990-01-01), Batty
patent: 4902533 (1990-02-01), White et al.
patent: 5060050 (1991-10-01), Tsuneoka et al.
patent: 5110712 (1992-05-01), Kessler et al.
patent: 5252516 (1993-10-01), Nguyen et al.

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