Static information storage and retrieval – Read/write circuit – Precharge
Patent
1997-12-18
1999-06-29
Nelms, David
Static information storage and retrieval
Read/write circuit
Precharge
36518911, G11C 700
Patent
active
059177675
ABSTRACT:
There is provided a semiconductor storage device which impairs neither sensing sensitivity nor sensing speed even when a number of memory cells are connected to an extension bit line. A boosting circuit boosts a voltage at an input node by a sensing sensitivity .DELTA.V by a boost signal from a selecting circuit, thereby providing a potential difference .DELTA.V between a voltage at the input node connected to a selected memory cell of a memory cell array and a voltage at an input node on a reference side. A sense amplifier amplifies the potential difference .DELTA.V between the input node and the input node up to a voltage. Thus, a sufficient sensing sensitivity can be obtained without reducing a pre-charge voltage at the input node to a reference voltage. Therefore, a sufficient sensing sensitivity and a rapidly sensing speed can be secured even with a great bit line resistance existence due to the connection of a number of memory cells to the extension bit line.
REFERENCES:
patent: 5623446 (1997-04-01), Hisada et al.
patent: 5703814 (1997-12-01), Nishimura et al.
"A High-speed Read Operation for Flash Memory Using Bit-line Clamped Sensing Scheme," by Y. Jyouno, T. Kawahara, S. Saeki, M. Miyamoto and K. Kimura, Conference of the Insitute of Electronics, Information and Communication Engineers, 1996.
Jyouno et al., "Study of flash memory high speed read operation using a bit line clamp method" Conference of the Institute of Electronics, Information and Communication Engineers (1996) 1 page total (English translation enclosed herewith, 4 pages total).
Nelms David
Sharp Kabushiki Kaisha
Tran M.
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