Dynamic random access memory with bit line preamp/driver

Static information storage and retrieval – Read/write circuit – Precharge

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365149, 365190, 365205, G11C 700

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active

054756421

ABSTRACT:
A preamp/driver circuit (18) is disclosed which is operable to interface a Bit Line (14) with a Data Line (20). The Bit Line (14) has a plurality of memory cells associated therewith which are selectable by Word Lines. The preamp/driver (18) decouples the Bit Line (14) from the Data Line (20) and drives Data Line (20) from a separate source. The preamp/driver (18) is comprised of a depletion transistor (22) that has the gate thereof connected to the Bit Line (14) and drives a source follower (26). The source follower (26) drives the Data Line (20) from the supply potential. The system is operable during a restore operation to write back to the Bit Line (14) from the Data Line (20) through a Write transistor (28). The restore operation is effected with a restore amplifier with the Read operation effected through a separate sensing device that converts the voltage on the Data Lines to full logic potentials.

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