Method and apparatus providing short latency round-robin arbitra

Details Method and apparatus providing short latency round-robin arbitra Method and apparatus providing short latency round-robin arbitra

1996-07-01

1999-11-16

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710119, 710120, G06F 1300

Patent

active

059875496

ABSTRACT:
Low-latency distributed round-robin arbitration is used to grant requests for access to a shared resource such as a computer system bus. A plurality of circuit board cards that each include two devices such as CPUs, I/O units, and ram and an address controller plugs into an Address Bus in the bus system. Each address controller contains logic implementing the arbitration mechanism with a two-level hierarchy: a single top arbitrator and preferably four leaf arbitrators. Each address controller is coupled to two devices and the logical "OR" of their arbitration request is coupled via an Arbitration Bus to other address controllers on other boards. Each leaf arbitrator has four prioritized request in lines, each such line being coupled to a single address controller serviced by that leaf arbitrator. By default, each leaf arbitrator and the top arbitrator implement a prioritized algorithm. However a last winner ("LW") state is maintained at every arbitrator that overrides the default, to provide round-robin selection. Each leaf arbitrator arbitrates among the zero to four requests it sees, selects a winner and signals the top arbitrator that it has a device wishing access. At the top arbitrator, if the first leaf arbitrator last won a grant, it now has lowest grant priority, and a grant will go to the next highest leaf arbitrator having a device seeking access.

REFERENCES:
patent: 4873626 (1989-10-01), Gifford
patent: 5396602 (1995-03-01), Amini

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