Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-10-29
2000-07-25
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438386, H01L 218242
Patent
active
060936002
ABSTRACT:
A method of fabricating a dynamic random-access memory (DRAM) device integrates a shallow trench isolation (STI) process and a storage node process into the fabrication of the DRAM device. With a bit line over capacitor (BOC) structure, the capacitor is laid out in parts of the shallow trench isolation structure to increase the surface area of the storage node by using the trench. During the fabrication of the capacitor, a stacked plug used to connect the bit line is formed. The stacked plug used as the interconnection in the circuit region is also formed. An insulating layer is formed to cover the capacitor, and an opening is formed therein to expose the stacked plug. A bit line and an interconnection are formed on the insulating layer to connect with a conducting layer which is located in the stacked plug and contacted with the source/drain regions.
REFERENCES:
patent: 5378907 (1995-01-01), Melzner
patent: 5585303 (1996-12-01), Hong et al.
patent: 5942778 (1999-08-01), Oikawa
patent: 5973346 (1999-10-01), Pan
patent: 6018177 (2000-01-01), Chi
Chen Terry Chung-Yi
Lee Tong-Hsin
Bowers Charles
Chen Jack
United Microelectronics Corp.
United Silicon Inc.
Wu Charles C.H.
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