Method of forming a gate which provides a reduced corner recess

Details Method of forming a gate which provides a reduced corner recess Method of forming a gate which provides a reduced corner recess

1999-06-28

2000-07-25

Pham, Long

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438296, 438424, 438789, 438790, H01L 218238

Patent

active

060935936

ABSTRACT:
The present invention provides a method for forming a gate which provides a reduced recess in an adjacent shallow trench isolation. The process begins by forming a shallow trench isolation on a semiconductor substrate having a cell area and an I/O area. The cell area is separated from the I/O area by the shallow trench isolation. A gate is formed on the cell area of the semiconductor substrate adjacent to the shallow trench isolation. Impurity ions are implanted into the semiconductor substrate adjacent to the gate to form source and drain regions. In a key step, a resist protect oxide layer having a greater porosity than the oxide of the shallow trench isolation, is deposited over the semiconductor substrate, the gate, and the shallow trench isolation. The resist protect oxide layer is patterned to form a resist protect oxide mask over the I/O area; thereby exposing the cell area. Because the resist protect oxide has a much higher etch rate than the oxide of the shallow trench isolation very little corner recessing takes place on the shallow trench isolation. Silicide regions are formed on the source and drain regions. Semiconductor fabrication continues using conventional process to form dielectric layers, contacts and interconnections.

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