Semiconductor programmable memory device and method of writing a

Details Semiconductor programmable memory device and method of writing a Semiconductor programmable memory device and method of writing a

1986-11-14

1988-05-10

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365200, G11C 1300

Patent

active

047440589

ABSTRACT:
A semiconductor programmable memory device, especially an E.sup.2 PROM, in which a checkerboard pattern for testing the operation of the memory matrix is easily written. The E.sup.2 PROM is provided with a circuit which can select all of the word lines or every other word line at the same time, and which can simultaneously select all of the bit lines. This circuit reduces the number of steps required to write a checkerboard pattern in the memory matrix to only four, regardless of the memory size. Therefore, the process time to write the checkerboard pattern is reduced to approximately 40 m sec, which is equivalent to the time required to write four bytes in the memory matrix.

REFERENCES:
patent: 4613957 (1986-09-01), Iwahashi

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