Method of fabricating vertical power MOSFET having low distribut

Details Method of fabricating vertical power MOSFET having low distribut Method of fabricating vertical power MOSFET having low distribut

1997-11-10

2000-03-28

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438138, 438268, 438614, H01L 21336, H01L 2144

Patent

active

060431253

ABSTRACT:
The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

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Suzuki, T., et al.: "Plated source bridge (PSB) GaAs power FET with improved reliability", 1981 IEEE MTT-S International Microwave Symposium Digest, Los Angeles, CA Jun., 1981, pp. 34-36, XP002034559.

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