Triple well flash memory fabrication process

Details Triple well flash memory fabrication process Triple well flash memory fabrication process

1997-05-27

2000-03-28

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, H01L 218247

Patent

active

060431237

ABSTRACT:
A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.

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