Trench random access memory cell and method of formation

Details Trench random access memory cell and method of formation Trench random access memory cell and method of formation

1995-09-28

1999-03-09

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438268, 438270, H01L 218242

Patent

active

058799710

ABSTRACT:
A method for forming a random access memory cell within four separate trench regions (106, 108, 110, and 112). One half of the memory cell has a first N-type transistor, which is a latch transistor (500), has a current electrode (101), a current electrode (126), and a gate electrode (114). A second N-type transistor, which is a word-line select transistor (504), has a first current electrode (101), a second current electrode (128), and a gate electrode (116). A P-channel pull up transistor (502) has a first current electrode (103), a second current electrode (124), and a gate electrode (114). The coupling of the electrodes (101 and 103) form a storage node of the one half of the memory cell which is contacted electrically by a conductive contact (140).

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