Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-10-31
1998-09-08
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257362, 257408, 257930, H01L 2362
Patent
active
058048600
ABSTRACT:
One embodiment of the instant invention is an electrostatic discharge protection device (10) which includes a field-effect transistor, the field-effect transistor comprising: a substrate (12) of a first conductivity type and having a surface and a backside; a gate structure (18) insulatively disposed on the substrate; a blocking region (30) disposed on the substrate and adjacent to the gate structure; a lightly-doped region (32) of a second conductivity type opposite the first conductivity type and disposed within the substrate and beneath the blocking region; a channel region (14) disposed within the substrate, under the gate structure, and adjacent the lightly-doped region; a first doped region (38) of the second conductivity type and disposed within the substrate and adjacent to the lightly doped region, the first doped region spaced away from the channel region by the lightly-doped region; and a second doped region (22) of the second conductivity type and disposed within the substrate, the second doped region spaced away from the first doped region by the channel region. Preferably, a first bipolar transistor (210) is integrated into the electrostatic discharge device and is formed by the substrate, the lightly-doped region and the second doped region and a second bipolar transistor (212) is integrated into the electrostatic discharge device and is formed by the substrate, the first doped region and the second doped region, the first bipolar transistor becoming conductive at a lower voltage during an ESD event than the second bipolar transistor but the second bipolar transistor able to carry more current during the ESD event.
REFERENCES:
patent: 5021853 (1991-06-01), Mistry
patent: 5606191 (1997-02-01), Wang
Ogura et al., "Design and Characteristics of the Lightly Doped Drain--Source (LDD) Insulated Gate Field--Effect Transistor", IEEE Transactions on Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1359-1367.
1988 EOS/ESD Symposium Proceedings, Effects of Interconnect Process and Snapback Voltage of the ESD Failure Threshold of NMOS Transistors, pp.212-219, by Kueing-Long Chen.,1988.
1995 IEE International Reliability Physics Proceedings, 33rd Annual, Las Vegas, Nevada, Apr. 4-6, 1995, IEEE Catalog No. 95CH3471-0, "Building-In ESD/EOS Reliability for Sub-Halfmicron CMOS Processes",pp. 276-283, by Carlos H. Diaz, Thomas E. Kopley and Paul J. Marcoux., 1995.
Brady III Wade James
Donaldson Richard L.
Mintel William
Texas Instruments Incorporated
Valetti Mark A.
LandOfFree
Integrated lateral structure for ESD protection in CMOS/BiCMOS t does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated lateral structure for ESD protection in CMOS/BiCMOS t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated lateral structure for ESD protection in CMOS/BiCMOS t will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1284220