Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

1997-03-19

1998-09-08

Wallace, Valencia Martin

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257301, 257302, 257305, H01L 27108, H01L 2976, H01L 2994

Patent

active

058048510

ABSTRACT:
A semiconductor memory device comprises a semiconductor substrate having a plurality of trenches selectively formed thereon, a plurality of capacitors formed in the trenches, each of the capacitors formed of the substrate, a capacitor insulating film formed on a surface of each of the trenches, and a storage node buried in each of the trenches interposing the capacitor insulating film, a plurality of transistors, formed on the substrate, for forming memory cells in relation to the plurality of capacitors, each of the transistors having a gate electrode formed on the substrate interposing a gate insulating film and source and drain regions formed in the substrate on both sides of the gate electrode, a plurality of element isolation films formed on side surfaces of upper portions of the trenches to surround the circumference thereof, respectively, the element isolation films having adjacent ones of the isolation films selectively coupled to each other such that at least one of the transistors is electrically insulated from another one of the transistors, and a plurality of conductive members, each connecting one of the source and drain regions of each of the transistors to the storage node of a corresponding one of the capacitors.

REFERENCES:
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patent: 5463236 (1995-10-01), Sakao
IEEE, 1992, pp. 803-806, Toshiyuki Nishihara, et al., "A Buried Capacitor DRAM cell with Bonded SOI for 256M and 1Gbit DRAMs".

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