Method of fabricating multi-stage read-only memory semiconductor

Details Method of fabricating multi-stage read-only memory semiconductor Method of fabricating multi-stage read-only memory semiconductor

1996-12-17

1998-09-08

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438130, H01L 218246

Patent

active

058044841

ABSTRACT:
A process for fabricating multi-stage memory cell units o semiconductor ROM device is disclosed. Each of the ROM device multi-stage memory cell units holds data bits that can be interpreted into any one of a number of voltage or current levels of more than two. The process is consisted of the steps of first forming a MOS transistor in the device substrate, and the transistor comprises a pair of source/drain regions and a gate structure. An insulating layer is then formed covering the transistor. A contact opening is then formed in each of the pair of source/drain regions. A resistor connecting across the source/drain regions of the transistor is then formed, and the resistor has each of its ends extending into corresponding one of the contact openings. Then, the memory cell unit is programmed at a first stage by optionally cutting or not cutting the resistor into electrically disconnected halves. In the second stage of programming, impurity ions are optionally implanted into the channel region underneath the transistor gate structure with or without the presence of a masking layer covering the channel region. Combinations of different resistance values in the source/drain resistor and different transistor channel region threshold voltages obtained in the first and second programming stages therefore comprise the multi-stage memory cell transistor threshold voltages for the ROM device.

REFERENCES:
patent: 4104784 (1978-08-01), Klein
patent: 4315781 (1982-02-01), Henderson
patent: 4608748 (1986-09-01), Noguchi et al.
patent: 5275959 (1994-01-01), Kobayashi et al.

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