Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-10-30
2000-11-21
Fourson, George
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438637, 438736, 430312, H01L 214763
Patent
active
061502561
ABSTRACT:
The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.
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Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Horak David V.
Rabidoux Paul A.
Fourson George
International Business Machines - Corporation
Shkurko Eugene I.
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