Shallow trench isolation method utilizing combination of spacer

Details Shallow trench isolation method utilizing combination of spacer Shallow trench isolation method utilizing combination of spacer

1999-07-22

2000-11-21

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438400, 438427, H01L 218242

Patent

active

06150212&

ABSTRACT:
A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.

REFERENCES:
patent: 5895253 (1999-04-01), Akram
patent: 5939333 (1999-08-01), Hurley et al.
patent: 5945704 (1999-08-01), Schrems et al.
patent: 5994209 (1999-11-01), Yieh et al.

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