Semiconductor memory device having cell array divided into a plu

Details Semiconductor memory device having cell array divided into a plu Semiconductor memory device having cell array divided into a plu

1997-10-28

1999-01-19

Mai, Son

Static information storage and retrieval

Read/write circuit

Precharge

36523003, 365190, G11C 700

Patent

active

058620907

ABSTRACT:
A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

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