Semiconductor devices and assemblies

Details Semiconductor devices and assemblies Semiconductor devices and assemblies

1998-05-01

2000-08-29

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438149, 438466, 257302, 156345, 156626, H01L 2100

Patent

active

061107654

ABSTRACT:
The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region. The invention also includes a method comprising: a) providing a semiconductive substrate; b) forming a conductivity-modifying diffusion region in only a portion of the substrate; c) forming an insulator layer over the semiconductive substrate; d) forming a semiconductive layer over the insulator layer; e) forming a depletion region within the semiconductive layer, the depletion region being proximate the insulator layer and having a different thickness over the conductivity-modifying diffusion region than over other portions of the substrate; and f) etching the semiconductive layer to about the depletion region.

REFERENCES:
patent: 5198379 (1993-03-01), Adan
patent: 5372673 (1994-12-01), Starger et al.
patent: 5482870 (1996-01-01), Inoue
patent: 5556503 (1996-09-01), Ogura
patent: 5618741 (1997-04-01), Young et al.
patent: 5650042 (1997-07-01), Ogura
patent: 5665613 (1997-09-01), Nakashima et al.
patent: 5807770 (1998-09-01), Mineji
patent: 5807772 (1998-09-01), Takemura
patent: 5844278 (1998-12-01), Mizuno et al.
patent: 5854509 (1998-12-01), Kunikiyo
patent: 5861336 (1999-01-01), Reedy et al.
patent: 5864162 (1999-01-01), Reedy et al.
patent: 5866468 (1999-02-01), Kono et al.
patent: 5895946 (1999-04-01), Hamamoto et al.
patent: 5930642 (1999-07-01), Moore et al.
patent: 5942781 (1999-08-01), Burr et al.
patent: 5994738 (1999-11-01), Wollesen
Ogura, A., "Control of Thickness Variation in Si-on-Insulator Bonded Wafers by Applying Voltage during KOH Etching", Jpn. J. Appl. Phys. vol. 35 (1996), pp. L71-L73, Part 2, No. 1B.

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