Split sense amplifier and staging buffer for wide memory archite

Details Split sense amplifier and staging buffer for wide memory archite Split sense amplifier and staging buffer for wide memory archite

1997-04-11

1999-11-23

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365205, 365208, G11C 1604

Patent

active

059912090

ABSTRACT:
In an amplifier design for a wide memory architecture, a staging buffer can be integrated with the final stage of a multi-stage sense amplifier. The staging buffer includes a memory latch for storing at least one bit of data. The data is transferred into the staging buffer from memory upon strobing at least one read enable line, and transferred from the staging buffer to a data bus upon strobing at least one write enable line. The data signal is transferred from the memory to the staging buffer at a voltage level lower than the full swing voltage level. The memory architecture produced using this design technique allows for a much lower voltage swing on all of the data lines, thus lowering the power requirements of the circuit.

REFERENCES:
patent: 5311469 (1994-05-01), Hoshi
patent: 5311471 (1994-05-01), Matsumoto
patent: 5341341 (1994-08-01), Fukuzo
patent: 5418737 (1995-05-01), Tran
patent: 5537352 (1996-07-01), Meyer
patent: 5726943 (1998-03-01), Yamagat

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