Differential amplifier with a latching function and a memory app

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

327 57, 326 62, G11C 700, H03K 19086

Patent

active

053734696

ABSTRACT:
A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.

REFERENCES:
patent: 5200651 (1993-04-01), Komatsu et al.

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