Memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365205, G11C 1140

Patent

active

044452039

ABSTRACT:
A memory device has memory cells for storing binary data, a data line coupled to the memory cells for transferring data stored in the memory cells, a decoder for selecting one of the memory cells to couple the selected memory cell with the data line, the potential of the data line being changed with the stored data of the selected memory cell, and a sense amplifier coupled to the data line for sensing the stored data of the selected memory cell and providing an output corresponding to the sensed stored data. The sense amplifier includes a sensor responsive to a first threshold level and a second threshold level for providing the output such that, when the data line potential crosses the first threshold level, the sensor provides an output representing the first stored data and when the data line potential crosses the second threshold level, the sensor provides an output representing second stored data.

REFERENCES:
patent: 3953839 (1976-04-01), Dennison et al.
patent: 4094008 (1978-06-01), Lockwood et al.
patent: 4123799 (1978-10-01), Peterson
patent: 4134151 (1979-01-01), O'Connell et al.

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